1. Field of the Invention
The present invention relates to an unbalance-to-balance converter for converting an unbalanced high frequency signal (UHF, microwaves, extreme high frequency, etc.) into a pair of balanced high frequency signals, and a balanced mixer for converting the frequency of the balanced high frequency signals.
2. Description of Related Art
FIG. 13 is a circuit diagram showing a conventional unbalance-to-balance converter disclosed in Japanese patent application laid-open No. 64-30316/1989, for example. In FIG. 13, the reference numeral 1 designates an input terminal 1 for inputting an unbalanced high frequency signal; 2 designates an FET that outputs, when the unbalanced high frequency signal is supplied to its gate terminal, balanced high frequency signals from its drain terminal and source terminal; 3 and 4 each designate an output terminal for producing one of the balanced high frequency signals; 5 designates a resistor with its first end connected to the gate terminal of the FET 2 and its second end connected to a power supply 6 that supplies a DC voltage; 7 designates a capacitor; 8 designates a resistor with its first end connected to the drain terminal of the FET 2 and its second end connected to a power supply 9 that supplies a DC voltage to the drain of the FET 2; 10 designates a capacitor; and 11 designates a resistor with its first end connected to the source terminal of the FET 2 and its second end connected to an earth conductor.
Next, the operation of the conventional unbalance-to-balance converter will be described.
First, an operational environment of the FET 2 will be described. The gate terminal of the FET 2 is connected to an earth conductor through the resistor 5 and power supply 6 or through the resistor 5 and capacitor 7. In this case, the power supply 6 is regarded as an open circuit and the capacitor 7 as a short circuit because the unbalanced signal applied to the input terminal 1 is a high frequency signal. (The impedance of a capacitor becomes nearly zero when the frequency of an input signal is high enough.) Thus, the load connected to the gate terminal of the FET 2 is assumed to be composed of only the resistor 5 at a high frequency.
On the other hand, the drain terminal of the FET 2 is connected to the earth conductor through the resistor 8 and power supply 9 or through the resistor 8 and capacitor 10. In this case, the power supply 9 is regarded as an open circuit and the capacitor 10 as a short circuit because the balanced signals output from the drain terminal of the FET 2 is a high frequency signal. Thus, the load connected to the drain terminal of the FET 2 is also assumed to be composed of only the resistor 8 at a high frequency.
In such an operational environment, the unbalanced high frequency signal applied to the input terminal 1 is supplied to the gate of the FET 2, and is amplified by the FET 2, so that the balanced high frequency signals are each output from its drain terminal and source terminal. The pair of the balanced high frequency signals are expected to have an identical amplitude and the opposite phases in an ideal case, in which the values of the resistors 8 and 11 are equal.
The drain and source of the FET 2, however, are not symmetrical in their structures, with different electrode areas in general. Thus, the drain side parasitic capacitance Cpd and source side parasitic capacitance Cps usually differ from each other (see, an equivalent circuit of the FET in FIG. 14), and their influence on the high frequency signals output from the drain terminal and source terminal grows with the increase in the difference between them.
More specifically, if the drain side parasitic capacitance Cpd differs from the source side parasitic capacitance Cps, the amplitudes of the two high frequency signals output from the drain terminal and source terminal will be unmatched, and their phases will shift from the complete opposition. Besides, the influence due to the difference between the two capacitances increases with the frequency of the input signal.
FIG. 15 shows a balanced mixer employing conventional unbalance-to-balance converters. An unbalance-to-balance converter 22 outputs balanced mixer input signals by unbalance-to-balance converting an unbalanced mixer input signal applied to an input terminal 21, and an unbalance-to-balance converter 24 outputs balanced local oscillator signals by unbalance-to-balance converting an unbalanced local oscillator signal applied to an input terminal 23. Thus, a mixer 25 is supplied with the balanced mixer input signals and the balanced local oscillator signals, and multiplies (mixes) them with preventing their leakage from an output terminal 26.
In summary, the conventional unbalance-to-balance converter with the foregoing arrangement has a problem in that the balanced signals output from the drain terminal and source terminal differ in amplitude and are not in complete opposition due to the difference between the drain side parasitic capacitance Cpd and source side parasitic capacitance Cps, and this phenomenon grows with an increase of the frequency of the input signal.
Furthermore, the conventional balanced mixer with the foregoing configuration has a problem in that the leakage power of the mixer input signals and local oscillator signals, which is included in the output from the output terminal 26, increases due to the unmatched amplitudes and incomplete opposition of the balanced signals output from the unbalance-to-balance converters 22 and 24.